ATC18RHA(2005) 查看數據表（PDF） - Atmel Corporation

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ATC18RHA
(Rev.:2005)

Rad. Hard 0.18 µm CMOS Cell-based ASIC for Space Use

Atmel Corporation 

4261B–AERO–06/05

ATC18RHA

• preliminary pin-out and floor-plan (*)

• max clock and data rates

• expected a.c. and d.c. characteristics

• expected static and dynamic consumption

• list of design tools at customer’s site

• package type

• logic review and design review dates

• prototypes availability date

(*) The availability of a preliminary net-list, pin-out and floor-plan will allow to run a detailed feasi-

bility study. It will consist of making some placement and routing trials with different tools in order

to determine the final flow and to anticipate as much tasks as possible prior to the reception of

the final net-list.

Depending on the available information, 2 types of feasibility study can be run: First level or

detailed feasibility study.

First level feasibility study will consist of estimating:

• design and support time

• die size

• package (type and cavity)

Detailed feasibility study will consist of:

• die size choice

• package (type and cavity) choice

• pin-out description

• first layout prototyping (**)

• placement

• clock tree generation

• routing

• static timing analysis (Atmel/Customer)

• choice of final flow

• design and support time

(**) This is performed in case of high timing criticality. It consists of running a fast place and

route to early evaluate the parasitic effects.

Placement, Clock Tree Generation (CTG) and routing may be performed with different tools (for

example, CTG could be made using CTPKS, FE/CTS or CTGen).

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