BD8166EFV-E2 查看數據表（PDF） - ROHM Semiconductor

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BD8166EFV-E2

12V Input Multi-channel System Power Supply IC

ROHM Semiconductor 

BD8166EFV

Technical Note

●Block Operation

 VREG

A block to generate constant-voltage for DC/DC boosting.

 VREF

A block that generates internal reference voltage of 2.9 V (Typ.).

 TSD/UVLO

TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block. The TSD circuit shuts down IC at 175°C (Typ.)

and recovers at 160°C (Typ.). The UVLO circuit shuts down the IC when the Vcc is 5.1 V (Typ.) or below.

 Error amp block (ERR)

This is the circuit to compare the reference voltage of 1.25 V (Typ.) and the feedback voltage of output voltage. The COMP

pin voltage resulting from this comparison determines the switching duty. At the time of startup, since the soft start is

operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage.

 Oscillator block (OSC)

This block generates the oscillating frequency.

 SLOPE block

This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to the

PWM comparator.

 PWM block

The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the

switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not

become 100%.

 DRV block

A DC/DC driver block. A signal from the PWM is input to drive the power FETs.

 CURRENT SENSE

Current flowing to the power FET is detected by voltage at the CURRENT SENSE and the overcurrent protection operates

at 3A (Typ.). When the overcurrent protection operates, switching is turned OFF and the SS pin capacitance is discharged.

 DELAY START

A start delay circuit for positive/negative charge pump.

 Soft start circuit

Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the

output voltage overshoot or the rush current.

 Positive charge pump

A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage

FB2 will be set to 1.25 V (Typ.).

The start delay time can be set in the DLS pin at the time of startup. When the DLS voltage reaches 0.65 V (Typ.),

switching waves will be output from the CL1 and CL2 pins.

 Negative charge pump

A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage

FB3 will be set to 1.25 V (Typ.).

 Gate shading controller

A controller circuit of gate shading. The Vo2GS and GSOUT are turned on and off according to IG pin input.

 VCOM

A common amplifier to set output voltage in a range of 0.3 V to Vo1-0.3 V.

 Timer latch

An output short protection circuit. If at least one output is down after the DC/DC2 and positive/negative charge pump

outputs all rise, all the outputs will be shut down.

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2015.12 - Rev.C

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