GS816273C 查看數據表（PDF） - Giga Semiconductor

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GS816273C

256K x 72 18Mb S/DCD Sync Burst SRAMs

Giga Semiconductor 

GS816273 BGA Pin Description

Symbol

A0, A1

An

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

DQD1–DQD9

DQE1–DQE9

DQF1–DQF9

DQG1–DQG9

DQH1–DQH9

BA, BB, BC,BD, BE, BF,

BG,BH

NC

CK

GW

E1, E3

E2

G

ADV

ADSP, ADSC

ZZ

LBO

SCD

MCH

MCL

Type

I

I

I/O

I

—

I

I

I

I

I

I

I

I

I

I

I

Preliminary

GS816273C-250/225/200/166/150/133

Description

Address field LSBs and Address Counter Preset Inputs.

Address Inputs

Data Input and Output pins

Byte Write Enable for DQA, DQB, DQC, DQD, DQE,

DQF, DQG, DQH I/Os; active low

No Connect

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Linear Burst Order mode; active low

Single Cycle Deselect/Dual Cycle Deselect Mode Control

Must Connect High

Must Connect Low

Rev: 1.01 12/2002

3/25

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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