CM88L70C 查看數據表（PDF） - California Micro Devices Corp
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CM88L70C Datasheet PDF : 8 Pages
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CALIFORNIA MICRO DEVICES
CM88L70/70C
Pin Function Table
Name
IN+
IN-
GS
VR E F
INH
OSC 3
PD
OSC1
OSC2
VS S
TOE
Q1
Q2
Q3
Q4
StD
ESt
St/Gt
VD D
IC
Description
Non-inverting input
Inverting input
Connection to the front-end differential amplifier
Gain Select. Gives access to output of front-end differential amplifier for connection
of feedback resistor.
Reference voltage output (nominally VD D /2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones represents keys A,B,C,D.
Digital buffered oscillator output.
Power down
Logic high powers down the device and inhibits the oscillator.
Clock input
Clock output
3.579545 MHz crystal connected between these pins completes internal oscillator.
Negative power supply (normally connected to 0V).
Three-state output enable (input). Logic high enables the outputs Q1 -Q4 . Internal pull-up.
Three-state outputs. When enabled by TOE, provides the code corresponding to the last
valid tone pair received. (See Fig. 2).
Delayed steering output. Presents a logic high when a received tone pair has been registered and the
output latch is updated. Returns to logic low when the voltage on St/GT falls below VT S t.
Early steering output. Presents a logic high immediately when the digital algorithm
detects a recognizable tone pair (signal condition). Any momentary loss of signal condition
will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VT S t detected at St causes the
device to register the detected tone pair and update the output latch. A voltage less than VT S t frees the
device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its
state is a function of ESt and the voltage on St. (See Fig. 2)
Positive power supply.
Internal connection. Must be tied to VSS (for 8870 configuration only)
CM88L70
CM88L70C
All resistors are ±1%tolerance.
All capacitors are ±5% tolerance.
Figure 1. Single Ended Input Configuration
FLOW
FHIGH KEY TOW Q4 Q3 Q2
Q1
697 1209
1
H
000
1
697 1336
2
H
0
0
10
697 1477
3
H
0
0
1
1
770 1209 4
H
0
10
0
770 1336 5
H
0
10
1
770 1477 6
H
0
1
10
852 1209 7
H
0
1
1
1
852 1336 8
H
10 0 0
852 1477 9
H
10 0
1
941 1209 0
H
10
10
941 1336
G
H
10
11
941 1477 #
H
1 10 0
697 1633 A
H
1 10
1
770 1633 B
H
1 1 10
852 1633 C
H
1111
941 1633 D
H
0
00
0
-
-
ANY L
Z
Z
Z
Z
L = Logic Low, H = Logic High, Z = High Impedance
Figure 2. Functional Diode Table
©2000 California Micro Devices Corp. All rights reserved.
6
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 8/16/2000
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