CY7C1311BV18(2004) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1311BV18 Datasheet PDF : 23 Pages
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PRELIMINARY
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Logic Block Diagram (CY7C1311BV18)
D[7:0] 8
A(18:0)
19
K
K
DOFF
Address
Register
CLK
Gen.
VREF
WPS
NWS[1:0]
Control
Logic
Logic Block Diagram (CY7C1911BV18)
D[8:0] 9
A(18:0)
19
K
K
DOFF
Address
Register
CLK
Gen.
VREF
WPS
BWS[0]
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
Read Data Reg.
32 16
16
Control
Logic
Reg.
Reg.
Reg.
8
RPS
C
C
CQ
CQ
8
Q[7:0]
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19 A(18:0)
Read Data Reg.
36 18
18
Control
Logic
Reg.
Reg.
Reg.
9
RPS
C
C
CQ
CQ
9
Q[8:0]
Document Number: 38-05620 Rev. **
Page 2 of 23
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