CY7C1311BV18-200BZI(2011) 查看數據表（PDF） - Cypress Semiconductor
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CY7C1311BV18-200BZI Datasheet PDF : 32 Pages
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CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
Application Example
Figure 1 shows four QDR-II used in an application.
Figure 1. Application Example
SRAM #1
R = 250ohms
ZQ
SRAM #4
ZQ R = 250ohms
Vt
RW B
D
PPW
SS S
CQ/CQ#
Q
R
A
# # # C C# K K#
RWB
P PW
D
SSS
CQ/CQ#
Q
A
# # # C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
Vt
Vt
R
Truth Table
The truth table for CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K RPS WPS
DQ
DQ
DQ
DQ
Write Cycle:
L-H H [8] L [9] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Load address on the rising
edge of K; write data on
two consecutive K and K
rising edges.
Read Cycle:
L-H
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
L [9] X Q(A) at C(t + 1) Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)
NOP: No Operation
L-H H H D = X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
D=X
Q = High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Previous State
Previous State
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 38-05620 Rev. *F
Page 11 of 32
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