Logic Block Diagram (CY7C1311BV18)
CY7C1311BV18, CY7C1911BV18
CY7C1313BV18, CY7C1315BV18
D[7:0]
8
A(18:0) 19
Address
Register
K
K
DOFF
VREF
WPS
NWS[1:0]
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19
A(18:0)
Read Data Reg.
32
16
16
Control
Logic
Reg.
Reg.
Reg. 8
8
8
8
RPS
C
C
8
CQ
CQ
Q[7:0]
Logic Block Diagram (CY7C1911BV18)
D[8:0]
9
A(18:0) 19
K
K
DOFF
VREF
WPS
BWS[0]
Address
Register
CLK
Gen.
Control
Logic
Write Write Write Write
Reg Reg Reg Reg
Address
Register
19
A(18:0)
Read Data Reg.
36
18
18
Control
Logic
Reg.
Reg.
Reg. 9
9
9
9
RPS
C
C
9
CQ
CQ
Q[8:0]
Document Number: 38-05620 Rev. *F
Page 2 of 32
[+] Feedback