CY7C1311BV18 查看數據表（PDF） - Cypress Semiconductor

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CY7C1311BV18

18-Mbit QDR™-II SRAM 4-Word Burst Architecture

Cypress Semiconductor 

CY7C1311BV18

CY7C1911BV18

CY7C1313BV18

CY7C1315BV18

Logic Block Diagram (CY7C1313BV18)

D[17:0] 18

A(17:0) 18

Address

Register

Write Write Write Write

Reg Reg Reg Reg

Address

Register

18 A(17:0)

K

K

DOFF

VREF

WPS

BWS[1:0]

CLK

Gen.

Control

Logic

Read Data Reg.

72 36

36

Logic Block Diagram (CY7C1315BV18)

D[35:0] 36

A(16:0) 17

Address

Register

Write Write Write Write

Reg Reg Reg Reg

Control

Logic

Reg.

Reg.

RPS

C

C

CQ

CQ

Reg.

18

18 Q[17:0]

Address

Register

17 A(16:0)

K

K

DOFF

VREF

WPS

BWS[3:0]

CLK

Gen.

Control

Logic

Read Data Reg.

144 72

72

Control

Logic

Reg.

Reg.

RPS

C

C

CQ

CQ

Reg.

36

36 Q[35:0]

Document Number: 38-05620 Rev. *C

Page 3 of 28

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