CY7C1311BV18 查看數據表（PDF） - Cypress Semiconductor
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CY7C1311BV18 Datasheet PDF : 28 Pages
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Definitions (continued)
Pin Name
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
NC/144M
NC/288M
VREF
VDD
VSS
VDDQ
I/O
Pin Description
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
Input
DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
Output TDO for JTAG.
Input
TCK pin for JTAG.
Input
TDI pin for JTAG.
Input
TMS pin for JTAG.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs
Reference as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18,
CY7C1315BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 8-bit data transfers in the case of
CY7C1311BV18, four 9-bit data transfers in the case of
CY7C1911BV18, four 18-bit data transfers in the case of
CY7C1313BV18, and four 36-bit data in the case of
CY7C1315BV18 transfers in two clock cycles.
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1313BV18 is described in the following sections. The
same basic descriptions apply to CY7C1311BV18,
CY7C1911BV18, and CY7C1315BV18.
Read Operations
The CY7C1313BV18 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise,
the corresponding lowest order 18-bit word of data is driven
onto the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data
Document Number: 38-05620 Rev. *C
Page 7 of 28
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