D78045H 查看數據表（PDF） - NEC => Renesas Technology
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D78045H Datasheet PDF : 58 Pages
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µPD78044H, 78045H, 78046H
FUNCTIONAL OUTLINE
Item
Product name
Internal
memory
ROM
Internal high-speed RAM
FIP display RAM
General registers
µPD78044H
µPD78045H
32K bytes
1024 bytes
40K bytes
48 bytes
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
µPD78046H
48K bytes
Instruction
cycle
For main system clock
For subsystem clock
Instruction set
I/O ports (including those
multiplexed with FIP pins)
Variable instruction execution time
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 5.0 MHz)
122 µs (at 32.768 kHz)
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit (set, reset, test, Boolean algebra)
Total
• CMOS input
• CMOS I/O
• N-ch open-drain
• P-ch open-drain I/O
• P-ch open-drain output
: 68 lines
: 2 lines
: 19 lines
: 13 lines
: 16 lines
: 18 lines
FIP controller/driver
A/D converter
Serial interface
Timer
Timer output
Clock output
Buzzer output
Total
: 34 lines
• Segments : 9 to 24 lines
• Digits
: 2 to 16 lines
• 8-bit resolution × 8 channels
• Power supply voltage: AVDD = 4.0 to 5.5 V
• 3-wire serial I/O mode : 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
3 lines (one for 14-bit PWM output)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(main system clock: when operating at 5.0 MHz)
32.768 kHz (subsystem clock: when operating at 32.768 kHz)
1.2 kHz, 2.4 kHz, 4.9 kHz (main system clock: when operating at 5.0 MHz)
Vectored
interrupt
Text input
Maskable interrupt
Non-maskable interrupt
Software interrupt
Internal 8 lines, external 4 lines
Internal 1 line
1 line
Internal 1 line
Power supply voltage
Package
VDD = 2.7 to 5.5 V
80-pin plastic QFP (14 × 20 mm)
4
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