DS1338(2004) 查看數據表（PDF） - Maxim Integrated
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DS1338 Datasheet PDF : 15 Pages
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DS1338 I2C RTC with 56-Byte NV RAM
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. See Figure 6 for the RTC
registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the
time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set
to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The clock can be halted whenever the
timekeeping functions are not required, which decreases VBAT current.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries
result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset
whenever the seconds register is written. Write transfers occur on the acknowledge from the DS1338. Once the
countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within
1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer,
provided the oscillator is already running.
Note that the initial power-on state of all registers, unless otherwise specified, is not defined. Therefore, it
is important to enable the oscillator (CH = 0) during initial configuration.
The DS1338 runs in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour
mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit, with logic
high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). If the 12/24-hour mode select is
changed, the hours register must be re-initialized to the new format.
On an I2C START, the current time is transferred to a second set of registers. The time information is read from
these secondary registers, while the clock continues to run. This eliminates the need to re-read the registers in
case of an update of the main registers during a read.
Figure 6. RTC and RAM Address Map
ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H–3FH
BIT 7
CH
0
0
0
0
0
OUT
BIT 6 BIT 5 BIT 4
12/24
10 Seconds
10 Minutes
AM/PM
10 Hour
10
Hour
0
0
0
0
10 Date
0
0
10
Month
10 Year
0
OSF SQWE
Note: Bits listed as “0” always read as a 0.
BIT 3
0
0
BIT 2 BIT 1
Seconds
Minutes
BIT 0
Hour
Day
Date
Month
Year
0
RS1 RS0
FUNCTION
Seconds
Minutes
Hours
Day
Date
Month
Year
Control
RAM 56 x 8
RANGE
00–59
00–59
1–12
+AM/PM
00–23
1–7
01–31
01–12
00–99
00H–FFH
10 of 15
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