DS28E01P-100-T 查看數據表（PDF） - Maxim Integrated
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DS28E01P-100-T Datasheet PDF : 21 Pages
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ABRIDGED DATA SHEET
DS28E01-100
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
PARASITE POWER
1-Wire NET
1-Wire FUNCTION
CONTROL
64-BIT
LASERED ROM
MEMORY AND
SHA-1 FUNCTION
CONTROL UNIT
512-BIT
SECURE HASH
ALGORITHM ENGINE
DS28E01-100
CRC-16
GENERATOR
DATA MEMORY
4 PAGES OF
256 BITS EACH
REGISTER
PAGE
64-BIT
SCRATCHPAD
SECRETS
MEMORY 64 BITS
Figure 1. Block Diagram
64-Bit Lasered ROM
Each DS28E01-100 contains a unique ROM registration
number that is 64 bits long. The first 8 bits are a 1-Wire
family code. The next 48 bits are a unique serial number.
The last 8 bits are a cyclic redundancy check (CRC) of
the first 56 bits. See Figure 3 for details. The 1-Wire CRC
is generated using a polynomial generator consisting of
a shift register and XOR gates as shown in Figure 4. The
polynomial is X8 + X5 + X4 + 1. Additional information
about the 1-Wire CRC is available in Application Note
27: Understanding and Using Cyclic Redundancy
Checks with Maxim iButton® Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the 48th bit of the serial number has been entered, the
iButton is a registered trademark of Maxim Integrated
Products, Inc.
6
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
Memory Access
The DS28E01-100 has four memory areas: data memo-
ry, secrets memory, register page with special function
registers and user bytes, and a volatile scratchpad. The
data memory is organized as four pages of 32 bytes.
Secret and scratchpad are 8 bytes each. The scratch-
pad acts as a buffer when writing to the data memory,
loading the initial secret, or when writing to the register
page.
Refer to the full data sheet for this information.
Maxim Integrated
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