28F160S3-160 查看數據表（PDF） - Intel

零件编号

产品描述 (功能)

生产厂家

28F160S3-160

WORD-WIDE FlashFile™ MEMORY FAMILY

Intel 

E

Commands are written using standard micro-

processor write timings. The CUI contents serve

as input to the WSM that controls the block

erase, programming, and lock-bit configuration.

The internal algorithms are regulated by the

WSM, including pulse repetition, internal

verification, and margining of data. Addresses

and data are internally latched during write

cycles. Writing the appropriate command outputs

array data, identifier codes, or Status Register

data.

Interface software that initiates and polls

progress of block erase, programming, and lock-

bit configuration can be stored in any block. This

code is copied to and executed from system

RAM during flash memory updates. After

successful completion, reads are again possible

via the Read Array command. Block erase

suspend allows system software to suspend a

block erase to read or write data from any other

block. Program suspend allows system software

to suspend a program to read data from any

other flash memory array location.

28F160S3, 28F320S3

2.1 Data Protection

Depending on the application, the system

designer may choose to make the VPP power

supply switchable or hardwired to VPPH1/2. The

device supports either design practice, and

encourages optimization of the processor-

memory interface.

When VPP ≤ VPPLK, memory contents cannot be

altered. When high voltage is applied to VPP, the

two-step block erase, program, or lock-bit

configuration command sequences provide

protection from unwanted operations. All write

functions are disabled when VCC voltage is below

the write lockout voltage VLKO or when RP# is at

VIL. The device’s block locking capability

provides additional protection from inadvertent

code or data alteration.

Figure 5. Memory Map

ADVANCE INFORMATION

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