VSC8102 查看數據表（PDF） - Vitesse Semiconductor
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VSC8102 Datasheet PDF : 14 Pages
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VITESSE
VSC8101/8102
Preliminary Data Sheet
155.52 Mb/s Clock and
Data Recovery Units
VSC8101/8102 AC Characteristics (Over recommended operating range
Parameter
Description
Min
Typ
Max Units
tCLK
tDCYC
REFCK+/- Input Clock period(1)
SDAT +/- Input data period
—
6.43
—
ns
tCLK -
30 ppm
—
tCLK +
30 ppm
∆ fDC
SDAT+/- Input Rate Difference with respect to
REFCK+/-
-30
—
+30
ppm
tCDC
REFCK+/- Duty Cycle
tDH
Recovered Data hold time from falling edge of
Recovered Clock(2)
40
—
60
%
2.5
—
3.9
ns
tDS
Recovered Data setup time to falling edge of
Recovered Clock(2)
2.5
—
3.9
ns
tRCH
RCLK+/- Recovered Clock Output High Pulse Width
2.6
—
—
ns
tRCL
RCLK+/- Recovered Clock Output Low Pulse Width
2.6
—
—
ns
tRCYC
RCLK+/- Recovered Clock Period
6.0
—
6.8
ns
tDJA
SDAT+/- Input Jitter Accommodation (DC to 20 MHz)
Peak-to-peak
—
—
3.2
ns
tLA
Lock Acquisition Time (3)
—
—
5.0
µs
Loop Bandwidth:
fBW
a) at FILTER0 = Lo
b) at FILTER0 = Hi
—
—
150
KHz
10
tRCJ
RCLK+/- Recovered Clock Jitter
-400
400
ps
tPD
Propagation Delay from SDATA+/- Input to RDAT+/-
Output
—
—
TBD
ps
tCr, tCf
REFCK+/- Input rise and fall time, 20% to 80%
—
—
1.2
ns
tSDr, tSDf
SDATA+/- Input rise and fall time, 20% to 80%
—
—
1.2
ns
tRCr, tRCf
RCLK+/- Recovered Clock Output rise and fall time,
20% to 80%
300
—
800
ps
tRDr, tRDf
RDAT+/- Recovered Data Output rise and fall time,
20% to 80%
300
—
800
ps
Notes: (1) The part is designed to operate at 155.52 MHz. A reference clock with frequency variation of +/- 50 ppm or better is rec-
ommended. Consult the factory for applications other than this frequency.
(2) With minimum 50% Input Data Eye opening at 155.52 Mb/s.
. (3) With a jitter-free data input and minimum transition density of 50%.
G52087-0 Rev. 1.3
® VITESSE Semiconductor Corporation
Page 3
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