MC10SX1401FJ 查看數據表（PDF） - Motorola => Freescale

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MC10SX1401FJ

155Mb/s / 622Mb/s Receiver (Demultiplexer) with Clock Recovery

Motorola => Freescale 

MC10SX1401

CONTROL LOGIC

DIFFERENTIAL

RX INPUT

RISP

POST

AMPLIFIER

RISN

ELECTRO–

OPTICAL

MODULE

DATA

DETECTION

AND

RETIMING

CLOCK

RECOVERY

PARALLEL

DATA

OUTPUT

ROD1:8

SERIAL

REP

TO

PARALLEL

ROC

OC3

(STM1)

OC12

(STM4)

Interface

MC10SX1401

Figure 2. MC10SX1401 Simplified Block Diagram

MX10SX1401 Theory of Operation

Operation of the SX1401 is straight forward. The device

recovers clock and data from the serial input. Serial–

to–parallel conversion is performed. Then the parallel data,

parity, and recovered clock is output. The bit–serial

622 Mbit/s or 155 Mbit/s data stream is converted into a

78 MByte/s or 19 MByte/s parallel data format.

The Data Clock is recovered from the incoming data

stream. No external reference clock is required. For testing

and applications which provide an external high–frequency

bit clock, the internal clock recovery circuit may be bypassed.

SX1401 Block Diagram Functional Description

Data Detection and Retiming

Receives the differential input signal and retimes the serial

data with the Recovered Clock.

The peak amplitude of the differential input signal is also

detected and a proportional Peak Detector Output (PDO) DC

voltage is output.

Clock Recovery

Using a standard phase locked loop (PLL) configuration,

the clock recovery circuit locks the output of an internal VCO

to the phase and frequency of the detected differential input

signal. The internal VCO operates nominally at 1.2GHz. The

output of the VCO is then divided to provide an internal

Recovered Clock at either 622MHz or 155MHz.

An Out Of Lock indicator (OOL) is driven HIGH if the PLL

is not locked.

Serial to Parallel Conversion

In OC3 mode, converts the retimed serial data into either a

4–bit (Nibble) or 8–bit (Byte) parallel format. This parallel

data is output to the ROD1:8 Bus. In Nibble mode, the data

appears on ROD2, 4, 6, 8.

In OC12 mode, the retimed serial data is converted into an

8–bit (Byte) parallel format. This parallel data is output to the

ROD1:8 Bus.

A parity bit is also generated from the retimed serial data

as it is shifted into the parallel register. the Receive Even

Parity Output (REP) is toggled whenever the current nibble

has EVEN parity.

The internal Recovered Clock is buffered and output as a

TTL Receive Output Data Clock (ROC) at 78MHz, 39MHz, or

19MHz, depending on the selected mode. Also output is a

PECL Differential Receiver Clock (RCKP/RCKM) at

155MHz.

SX1401 Control Signals

Reset (RSTN) – Used for testing and verification, the TTL

outputs are set to Tri–State and all divider flip–flops are

reset by applying RSTN LOW. An internal pull–up is

provided on RSTN allowing the device to operate

normally if RSTN is not used.

Low Speed Select (LSS) – Selects data rate. LOW = OC–12

(622.08 Mb/s), HIGH = OC–3 (155.52 Mb/s). An

internal pull–up is provided on LSS allowing the device

to operate in OC–12 mode if LSS is not used.

Byte / Nibble Select (BYTE) – In OC–3 mode, selects

between 4–bit (Nibble) and 8–bit (Byte) parallel data

output format. LOW = Nibble, HIGH = Byte. An internal

pull–up is provided on BYTE allowing the device to

operate in Byte mode if BYTE is not used.

MOTOROLA

2

ECLinPS and ECLinPS Lite

DL140 — Rev 3

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