CXB1575AQ 查看數據表（PDF） - Sony Semiconductor

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CXB1575AQ

155Mbps Clock & Data Recoverywith High Sensitivity Limiting Amplifier

Sony Semiconductor 

CXB1575AQ

2. Alarm block

This block provides a signal interruption alarm output used for open fibre control (OFC).

Signal detect threshold level and hysteresis width are both user adjustable.

Signal detect threshold default level is 18mVp-p (single-ended).

An external resister Rd between DOWN and VCCR decrease it.

Typical characteristics of Rd vs. threshold level is shown in fig. 7, 8.

Hysteresis width can be also decreased by an external resister RH. Typical characteristics of RH vs. ∆P is

shown in fig. 9.

Timing chart of signal detect function is shown in fig. 5. SD response assert/deassert time are decided by peak

hold capacitor CR and CS.Their typical value is 470pF for 155Mbps operation.

Rd Rh

17 16 15

Cs CR

14 13 12

Cs : 470pF

CR : 470pF

Fig. 3

High

level

VDAS → Deassert level

VAS → Assert level

Low

level

VDAS

Small

3dB 3dB

Alarm setting

input level

VAS

Large

Hysteresis

Input electrical signal amplitude

Fig. 4

Data input

(D)

Alarm output

(SDEN)

Alarm output

(SDE, SDC)

Assert time

Deassert time

Fig. 5. Timing Chart

– 12 –

Hysteresis width

Alarm setting level

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