CXB1575AQ 查看數據表（PDF） - Sony Semiconductor

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CXB1575AQ

155Mbps Clock & Data Recoverywith High Sensitivity Limiting Amplifier

Sony Semiconductor 

CXB1575AQ

3. Clock and Data recovery block

Clock recovery is reallized by fully integrated phase locked loop (PLL), which needs no external reference clock.

PLL accepts scrambled NRZ data with 50% mark density. Two external components Re and Cp are required.

Their recommended values are shown in fig. 6.

Cp

30 29 27 26 25

31

Re

Fig. 6

Re :1.8k Ω

Cp :0.68µF (155.52Mbps)

Re is a resistor which decides VCO center frequency. To reduce the temperature dependence of the VCO

oscillation frequency, Re should have a small temperature coefficient. In addition, Re should place as near as

IC terminal to obtain good jitter performance.

Cp is a loop filter capacitance. Since loop damping factor ξ is function of √Cp, Cp is also important to have a

small temperature coefficient. Damping factor ξ is given as

20,000 × √Cp (@ρ = 1/2) ∗3

Recommended Cp value gives a ξ of 10, and jitter peaking of under 0.1dB is specified.

∗3 ρ: data transition density

4. Others

Pay attention to handling this IC because its electrostatic discharge strength is weak.

– 13 –

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