FM3204 查看數據表（PDF） - Unspecified

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FM3204

Integrated Processor Companion with Memory

Unspecified 

FM3204/16/64/256

09h

WTR

POR

LB

WR3-0

00-08h

Watchdog Restart & Flags

D7

D6

D5

D4

D3

D2

D1

D0

WTR

POR

LB

-

WR3

WR2

WR1

WR0

Watchdog Timer Reset Flag: When the /RST signal is activated by the watchdog the WTR bit will be set to 1. It

must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since

the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).

Power-on Reset Flag: When the /RST pin is activated by either VDD < VTP or a manual reset, the POR bit will be

set to 1. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have

occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit).

Low Backup Flag: On power up, if the VBAK source is below the minimum voltage to operate the event counters,

this bit will be set to 1. The user should clear it to 0 when initializing the system. Battery-backed. Read/Write

(internally set, user can clear bit).

Watchdog Restart: Writing a pattern 1010b to WR3-0 restarts the watchdog timer. The upper nibble contents do

not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the timer. This allows

users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Write-only.

Reserved – DO NOT USE THIS ADDRESS SPACE

Rev 2.1

Dec. 2004

Page 10 of 20

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