HC1S25 查看數據表（PDF） - Altera Corporation

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HC1S25

HardCopy Stratix Device Family

Altera Corporation 

HardCopy Series Handbook, Volume 1

Table 1–1. HardCopy Stratix Devices and Features

Device

HC1S25

HC1S30

HC1S40

HC1S60

HC1S80

LEs (1)

25,660

32,470

41,250

57,120

79,040

M512 Blocks M4K Blocks

224

138

295

171

384

183

574

292

767

364

M-RAM

Blocks

2

2 (4)

2 (4)

6

6 (4)

DSP Blocks (2)

10

12

14

18

22

PLLs (3)

6

6

6

12

12

Notes to Table 1–1:

(1) LE: logic elements.

(2) DSP: digital signal processing.

(3) PLLs: phase-locked loops.

(4) In HC1S30, HC1S40, and HC1S80 devices, there are fewer M-RAM blocks than in the equivalent Stratix FPGA. All

other resources are identical to the Stratix counterpart.

Features

HardCopy Stratix devices are manufactured on the same 1.5-V, 0.13 μm

all-layer-copper metal fabrication process (up to eight layers of metal) as

the Stratix FPGAs.

■ Preserves the functionality of a configured Stratix device

■ Pin-compatible with the Stratix counterparts

■ On average, 50% faster than their Stratix equivalents

■ On average, 40% less power consumption than their Stratix

equivalents

■ 25,660 to 79,040 LEs

■ Up to 5,658,408 RAM bits available

■ TriMatrix memory architecture consisting of three RAM block sizes

to implement true dual-port memory and first-in-first-out (FIFO)

buffers

■ Embedded high-speed DSP blocks provide dedicated

implementation of multipliers, multiply-accumulate functions, and

finite impulse response (FIR) filters

■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device

which provide identical features as the FPGA counterparts,

including spread spectrum, programmable bandwidth, clock

switchover, real-time PLL reconfiguration, advanced multiplication,

and phase shifting

■ Supports numerous single-ended and differential I/O standards

■ Supports high-speed networking and communications bus

standards including RapidIO™, UTOPIA IV, CSIX, HyperTransport

technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4),

and SFI-4

■ Differential on-chip termination support for LVDS

1–2

Preliminary

Altera Corporation

September 2008

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