HDD16M64B8-13A 查看數據表（PDF） - Hanbit Electronics Co.,Ltd

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HDD16M64B8-13A

DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8, 4Banks, 4K Ref. SO-DIMM

Hanbit Electronics Co.,Ltd 

HANBit

HDD16M64B8

PIN FUNCTION DESCRIPTION

Pin

CK, /CK

CKE

/CS

A0 ~ A11

BA0 ~ BA1

/RAS

/CAS

/WE

DQS0 ~ 7

DM0~7

Name

Input Function

CK and CK are differential clock inputs. All address and control input signals are

Clock

sam-pled on the positive edge of CK and negative edge of CK. Output (read) data

is referenced to both edges of CK. Internal clock signals are derived from CK/CK.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides

PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or

Clock Enable

ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all

functions except for disabling outputs, which is achieved asynchronously. Input

buffers, excluding CK, CK and CKE are disabled during power-down and self

refresh modes, providing low standby power. CKE will recognizean LVCMOS

LOW level prior to VREF being stable on power-up.

CS enables(registered LOW) and disables(registered HIGH) the command

decoder.

Chip Select

All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the

command code.

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

Bank select address

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE

command is being applied.

Row address strobe

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

Column

strobe

address Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

Write enable

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

Data Strobe

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DM is an input mask signal for write data. Input data is masked when DM is

Input Data Mask

sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. DM pins include dummy loading internally, to matches the

DQ and DQS load-ing.

DQ0 ~ 63

VDDQ

VDD

VSS

VREF

VSPD

VDDID

Data input/output

Supply

Supply

Supply

Supply

Supply

Data inputs/outputs are multiplexed on the same pins.

DQ Power Supply : +2.5V ± 0.2V.

Power Supply : +2.5V ± 0.2V (device specific).

DQ Ground.

SSTL_2 reference voltage.

Serial EEPROM Power Supply : 3.3v

VDD identification Flag

URL : www.hbe.co.kr

REV 1.0 (August. 2002)

4

HANBit Electronics Co.,Ltd.

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