HDD16M72D9RPW 查看數據表（PDF） - Hanbit Electronics Co.,Ltd

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HDD16M72D9RPW

DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with PLL & Register

Hanbit Electronics Co.,Ltd 

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HDD16M72D9RPW

PIN FUNCTION DESCRIPTION

Pin

Name

CK, /CK Clock

CKE

Clock Enable

/CS

Chip Select

A0 ~ A12 Address

BA0 ~ BA1 Bank select address

/RAS

Row address strobe

/CAS

Columnaddress strobe

/WE

Write enable

DQS0 ~ 7 Data Strobe

DM0~7

Input Data Mask

Input Function

CK and /CK are differential clock inputs. All address and control input signals are

sampled on the positive edge of CK and negative edge of CK. Output (read) data

is referenced to both edges of CK. Internal clock signals are derived from CK/CK.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Deactivating the clock provides

PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE

POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions

except for disabling outputs, which is achieved asynchronously. Input buffers,

excluding CK, CK and CKE are disabled during power-down and self refresh

modes, providing low standby power. CKE will recognizean LVCMOS LOW level

prior to VREF being stable on power-up.

/CS enables(registered LOW) and disables(registered HIGH) the command

decoder.

All commands are masked when /CS is registered HIGH. /CS provides for external

bank selection on systems with multiple banks. /CS is considered part of the

command code.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE

command is being applied.

Latches row addresses on the positive going edge of the CLK with /RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with /CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. DM pins include dummy loading internally, to matches the

DQ and DQS load-ing.

DQ0 ~ 63 Data input/output

WP

VDDQ

VDD

VSS

VREF

Write Protection

Supply

Supply

Supply

Supply

Data inputs/outputs are multiplexed on the same pins.

WP pin is connected to Vcc.

When WP is “high”, EEPROM Programming will be inhibited and the entire

memory will be write-protected.

DQ Power Supply : +2.5V ± 0.2V.

Power Supply : +2.5V ± 0.2V (device specific).

DQ Ground.

SSTL_2 reference voltage.

URL : www.hbe.co.kr

REV 1.0 (November.2002)

4

HANBit Electronics Co.,Ltd.

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