HM64YLB36514 查看數據表（PDF） - Renesas Electronics
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产品描述 (功能)
生产厂家
HM64YLB36514
Renesas Electronics
HM64YLB36514 Datasheet PDF : 22 Pages
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HM64YLB36514 Series
Pin Descriptions
Name
V
DD
VSS
VDDQ
VREF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
I/O type Descriptions
Supply Core power supply
Supply Ground
Supply Output power supply
Supply Input reference, provides input reference voltage
Input Clock input, active high
Input Clock input, active low
Input Synchronous chip select
Input Synchronous write enable
Input Synchronous address input
Input Synchronous byte write enables
Input Asynchronous output enable
Input Power down mode select
Input Output impedance control
I/O
Synchronous data input/output
M1, M2 Input
TMS Input
TCK Input
TDI
Input
TDO Output
NC
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
Notes
n: 0 to 18
x: a to d
1
x: a to d
n: 0 to 8
M1
M2
Protocol
Notes
V
V
Synchronous register to latch operation
2
DD
SS
Notes:
1.
ZQ
is
to
be
connected
to
V
SS
via
a
resistance
RQ
where
175
Ω
≤
RQ
≤
300
Ω.
If ZQ = V or
DDQ
open, output buffer impedance will be maximum.
2. There is 1 protocol with mode control input pins (M1, M2). These mode pins are to be tied either
V or V respectively.
DD
SS
These mode pins are set at power-up and will not change the states during the SRAM operates.
This SRAM is tested only in the synchronous register to latch operation.
Rev.0.10, May.15.2003, page 4 of 22
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