83940AY-02 查看數據表（PDF） - Integrated Device Technology
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83940AY-02 Datasheet PDF : 15 Pages
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ICS83940-02
LOW SKEW, 1-TO-18
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83940AY-02
www.idt.com
8
REV. A AUGUST 4, 2010
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