FCT162511AT(2001) 查看數據表（PDF） - Integrated Device Technology

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FCT162511AT
(Rev.:2001)

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

Integrated Device Technology 

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

FAST CMOS 16-BIT

IDT54/74FCT162511AT/CT

REGISTERED/LATCHED

TRANSCEIVER WITH PARITY

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical tsk(o) (Output Skew) < 250ps, clocked mode

• Low input and output leakage ≤1µA (max)

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 5V ±10%

• Balanced Output Drivers:

– ±24mA (industrial)

– ±16mA (military)

• Series current limiting resistors

• Generate/Check, Check/Check modes

• Open drain parity error allows wire-OR

• Available in the following packages:

– Industrial: SSOP, TSSOP

– Military: CERPACK

DESCRIPTION:

The FCT162511T 16-bit registered/latched transceiver with parity is built

using advanced dual metal CMOS technology. This high-speed, low-power

transceiver combines D-type latches and D-type flip-flops to allow data flow in

transparent, latched, or clocked modes. The device has a parity generator/

checker in the A-to-B direction and a parity checker in the B-to-A direction. Error

checking is done at the byte level with separate parity bits for each byte. Separate

error flags exits for each direction with a single error flag indicating an error for

either byte in the A-to-B direction and a second error flag indicating an error for

either byte in the B-to-A direction. The parity error flags are open drain outputs

which can be tied together and/or tied with flags from other devices to form a single

error flag or interrupt. The parity error flags are enabled by the OExx control

pins allowing the designer to disable the error flag during combinational

transitions.

The control pins LEAB, CLKAB, and OEAB control operation in the A-to-B

direction while LEBA, CLKBA, and OEBA control the B-to-A direction. GEN/

CHK is only for the selection of A-to-B operation. The B-to-A direction is always

in checking mode. The ODD/EVEN select is common between the two directions.

Except for the ODD/EVEN control, independent operation can be achieved

between the two directions by using the corresponding control lines.

FUNCTIONAL BLOCK DIAGRAM

LEAB

CLKAB

G E N /C H K

A0-15

PA1,2

ODD/EVEN

Data

16

Byte

Parity

Generator/

Checker

Parity

2

Latch/

R e g iste r

Parity, data

18

OEBA

PERA

(Open Drain)

Parity, data

18

Latch/

Register

Parity, Data

18

Byte

Parity

Checking

OEAB

B0-15

PB1,2

PERB

(Open Drain)

LEBA

CLKBA

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND INDUSTRIAL TEMPERATURE

1

© 2001 Integrated Device Technology, Inc.

RANGES

MAY 2001

DSC-2916/-

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