IDT54FCT810BTDB 查看數據表（PDF） - Integrated Device Technology
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IDT54FCT810BTDB Datasheet PDF : 6 Pages
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IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT54/74FCT810BT
IDT54/74FCT810CT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
tPLH Propagation Delay
tPHL INA to OAn, INB to OBn
tR
Output Rise Time
Condition(1) Min.(2)
CL = 50pF 1.5
RL = 500Ω
—
Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
4.5 1.5 4.9 1.5 4.3 1.5 4.6
1.5 — 2.0 — 1.5 — 2.0
Unit
ns
ns
tF
Output Fall Time
— 1.5 — 1.5 — 1.5 — 1.5 ns
tSK1(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
— 0.5 — 0.9 — 0.3 — 0.7 ns
tSK2(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
— 0.7 — 1.1 — 0.6 — 1.0 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output |(tPHL-tPLH)|
— 0.7 — 1.2 — 0.7 — 1.1 ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
— 1.2 — 1.5 — 1.0 — 1.2 ns
tPZL Output Enable Time
tPZH OEA to OAn, OEB to OBn
1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
tPLZ Output Disable Time
tPHZ OEA to OAn, OEB to OBn
1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
NOTES:
3103 tbl 06
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.4
4
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