IDT6168SA45 查看數據表（PDF） - Integrated Device Technology
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IDT6168SA45 Datasheet PDF : 7 Pages
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IDT6168SA/LA
CMOS STATIC RAM 16K (4K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 5)
ADDRESS
CS
tAS
WE
DATAIN
t WC
t AW
tCW
tWR(3)
t DW
t DH
DATA VALID
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals should not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high impedance state.
6. Transition is measured ±200mV from steady state.
3090 drw 09
ORDERING INFORMATION
IDT 6168
Device
Type
XX
Power
XXX
Speed
XX
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
300mil Plastic DIP (P20-1)
D
300mil Ceramic DIP (D20-1)
SO 300mil Small Outline IC, Gull Wing (SO20-2)
15
20
25
35
45
Military Only
Speed in nanoseconds
SA
Standard Power
LA
Low Power
3090 drw 10
5.3
7
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