IDT72413(2003) 查看數據表（PDF） - Integrated Device Technology

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IDT72413
(Rev.:2003)

CMOS PARALLEL FIFO WITH FLAGS 64 x 5

Integrated Device Technology 

IDT72413 CMOS PARALLEL FIFO WITH FLAGS

64 x 5

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns

1.5V

1.5V

See Figure 1

2748 tbl 07

STANDARD TEST LOAD

5V

OUTPUT

R1

TEST POINT

R2

30pF*

DESIGN TEST LOAD

5V

2K‰

30pF*

or equivalent circuit

*Including scope and jig

2748 drw 03

RESISTOR VALUES FOR

STANDARD TEST LOAD

IOL

24mA

12mA

8mA

R1

200Ω

390Ω

600Ω

Figure 1. Output Load

R2

300Ω

760Ω

1200Ω

FUNCTIONAL DESCRIPTION:

The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture

as opposed to the traditional shift register approach. This FIFO architecture has

a write pointer, a read pointer and control logic, which allow simultaneous read

and write operations. The write pointer is incremented by the falling edge of the

Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift

Out (SO). The Input Ready (IR) signals when the FIFO has an available

memory location; Output Ready (OR) signals when there is valid data on the

output. Output Enable (OE) provides the capability of three-stating the FIFO

outputs.

FIFO RESET

The FIFO must be reset upon power up using the Master Reset (MR) signal.

This causes the FIFO to enter an empty state signified by Output Ready (OR)

being LOW and Input Ready (IR) being HIGH. In this state, the data outputs

(Q0-4) will be LOW.

DATA INPUT

Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads

input data into the first word location of the FIFO and causes the lnput Ready

(IR) to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved

to the next word position and lR goes HlGH indicating the readiness to accept

new data. If the FIFO is full, IR will remain LOW until a word of data is shifted

out.

DATA OUTPUT

Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes

the internal read pointer to be advanced to the next word location. If data is

present, valid data will appear on the outputs and Output Ready (OR) will go

HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The

last valid word read from the FIFO will remain at the FlFOs output when it is empty.

When the FIFO is not empty OR goes LOW on the LOW-to-HlGH transition of

SO.

FALL-THROUGH MODE

The FIFO operates in a Fall-Through Mode when data gets shifted into an

empty FIFO. After the fall-through delay the data propagates to the output. When

the data reaches the output, the Output Ready (OR) goes HIGH.

A Fall-Through Mode also occurs when the FIFO is completely full. When

data is shifted out of the full FIFO a location is available for new data. After a fall-

through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data

can be written to the FIFO. The fall-through delay of a RAM-based FIFO (one

clock cycle) is far less than the delay of a Shift register-based FIFO.

SIGNAL DESCRIPTIONS:

INPUTS:

DATA INPUT (D0-4)

Data input lines. The IDT72413 has a 5-bit data input.

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