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IDT72413(2003) 查看數據表(PDF) - Integrated Device Technology

零件编号
产品描述 (功能)
生产厂家
IDT72413
(Rev.:2003)
IDT
Integrated Device Technology IDT
IDT72413 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
COMMERCIAL TEMPERATURE RANGE
CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
can be written to the FIFO via the D0-4 lines. The data has to meet set-up and
hold time requirements with respect to the rising edge of SI.
SHIFT OUT (SO)
Shift Out controls the outputs data from the FIFO.
OUTPUT READY (OR)
When Output Ready is HIGH, the output (Q0-4) contains valid data. When
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FIFOs together, as shown in Figure 13.
OUTPUT ENABLE (OE)
Output Enable is used to enable the FIFO outputs onto a bus. OE is active
LOW.
MASTER RESET (MR)
Master Reset clears the FIFO of any data stored within. Upon power up, the
FIFO should be cleared with a Master Reset. Master Reset is active LOW.
ALMOST-FULL/EMPTY FLAG (AF/E)
Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words)
or 1/8 from empty (8 or less words).
HALF-FULL FLAG (HF)
Half-Full Flag signals when the FIFO has 32 or more words in it.
INPUT READY (IR)
When Input Ready is HIGH, the FIFO is ready for new input data to be written
to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also
used to cascade many FIFOs together, as shown in Figure 13.
OUTPUTS:
DATA OUTPUT (Q0-4)
Data output lines, three-state. The IDT72413 has a 5-bit output.
SI
IR
tIDS
INPUT DATA
tSIH
tIDH
1/fIN
tSIL
1/fIN
tIRH
tIRL
Figure 2. Input Timing
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SI (7)
(2)
(4)
(1)
IR
(3)
INPUT DATA
STABLE DATA
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the FIFO.
3. IR goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
Figure 3. The Machanism of Shifting Data Into the FIFO
5
(5)
(6)
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