IDT72413(2003) 查看數據表（PDF） - Integrated Device Technology

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IDT72413
(Rev.:2003)

CMOS PARALLEL FIFO WITH FLAGS 64 x 5

Integrated Device Technology 

IDT72413 CMOS PARALLEL FIFO WITH FLAGS

64 x 5

OUTPUT

ENABLE

HF OE AF/E

IR

SO

SI

OR

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4 MR Q4

COMMERCIAL TEMPERATURE RANGE

SHIFT OUT

COMPOSITE

INPUT

READY

HF OE AF/E

IR

SO

SI

OR

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4 MR Q4

COMPOSITE

OUTPUT

READY

SHIFT IN

HF OE AF/E

IR

SO

SI

OR

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4 MR Q4

MASTER

RESET

2748 drw 15

NOTE:

1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement

is due to the different fall-through times of the FIFOs.

Figure 13. 64 x 15 FIFO with IDT72413

SYSTEM 1

ENBL SI

8-BITS

TWO

IDT72413

64 x 8

SI

SO

IR

OR

8-BITS

SYSTEM 2

IO RDY

INTERRUPT

ALMOST-FULL/

EMPTY

INTERRUPT

HALF-FULL FLAG

NOTE:

1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.

2748 drw 16

Figure 14. Application for IDT72413 for Two Asynchronous Systems

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