IDT72413(2003) 查看數據表（PDF） - Integrated Device Technology

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IDT72413
(Rev.:2003)

CMOS PARALLEL FIFO WITH FLAGS 64 x 5

Integrated Device Technology 

IDT72413 CMOS PARALLEL FIFO WITH FLAGS

64 x 5

(2)

SO

SI

IR (1)

(3)

tPT

COMMERCIAL TEMPERATURE RANGE

(5)

tIPH

(4)

INPUT DATA

STABLE DATA

NOTES:

1. FIFO is initially full.

2. SO pulse is applied.

3. SI is held HIGH.

4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.

5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

2748 drw 06

SO(7)

(2)

(1)

OR

OUTPUT DATA

(3)

A- DATA

(4)

(5)

A or B

NOTES:

1. This data is loaded consecutively A, B, C.

2. Output data changes on the falling edge of SO after a valid SO sequence, i.e., OR and SO are both HIGH together.

Figure 5. Output TIming

(6)

B- DATA

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tSOH

1/fOUT

tSOL

SO

1/fOUT

(2)

OR

OUTPUT DATA

tORD

(1)

A-DATA

tODS

tODH

tRH

tORL

B-DATA

NOTES:

1. OR HIGH indicates that data is available and a SO pulse may be applied.

2. SO goes HIGH causing the next step.

3. OR goes LOW.

4. Read pointer is incremented.

5. OR goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns.

6. If the FIFO has only one word loaded (A DATA) , OR stays LOW and the A-DATA remains unchanged at the outputs.

7. SO pulses applied when OR is LOW will be ignored.

Figure 6. The Mechanism of Shifting Data Out of the FIFO

6

C-DATA

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