IDT72413 查看數據表（PDF） - Integrated Device Technology

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IDT72413

CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

Integrated Device Technology 

IDT72413

CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:

INPUTS:

DATA INPUT (D0-4)

Data input lines. The IDT72413 has a 5-bit data input.

CONTROLS:

SHIFT IN (SI)

Shift In controls the input of the data into the FIFO. When

SI is HIGH, data can be written to the FIFO via the D0-4 lines.

The data has to meet set-up and hold time requirements with

respect to the rising edge of SI.

INPUT READY(IR)

When Input Ready is HIGH, the FIFO is ready for new input

data to be written to it. When IR is LOW, the FIFO is

unavailable for new input data, Input Ready is also used to

cascade many FIFOs together, as shown in Figure 13 in the

Applications section.

OUTPUT READY (OR)

When Output Ready is HIGH, the output (Q0-4) contains valid

data. When OR is LOW, the FIFO is unavailable for new

output data. Output Ready is also used to cascade many

FIFOs together, as shown in Figure 13 in the Applications

section.

SHIFT OUT (SO)

Shift Out controls the outputs data from the FIFO.

MASTER RESET (MR)

Master Reset clears the FIFO of any data stored within.

Upon power up, the FIFO should be cleared with a Master

Reset. Master Reset is active LOW.

OUTPUT ENABLE (OE)

Output Enable is used to enable the FIFO outputs onto a

bus. Output Enable is active LOW.

ALMOST-FULL/EMPTY FLAG (AFE)

Almost-Full/Empty Flag signals when the FIFO is 7/8 full

(56 or more words) or 1/8 from empty (8 or less words).

HALF-FULL FLAG (HF)

Half-Full Flag signals when the FIFO has 32 or more words

in it.

TIMING DIAGRAMS

1/fIN

OUTPUTS:

DATA OUTPUT (Q0-4)

Data output lines, three-state. The IDT72413 has a 5-bit

output.

1/fIN

SHIFT IN

tSIH

t SIL

INPUT READY

INPUT DATA

t IDH

t IDS

tIRH

tIRL

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Figure 2. Input Timing

SHIFT IN(7)

INPUT READY

(2)

(1)

(4)

(5)

(3)

INPUT DATA

STABLE DATA

Figure 3. The Machanism of Shifting Data Into the FIFO

NOTES:

1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.

2. Input Data is loaded into the FIFO.

3. Input Ready goes LOW indicating the FIFO is unavailable for new data.

4. The write pointer is incremented.

5. The FIFO is ready for the next word.

6. If the FIFO is full, then the Input Ready remains LOW.

7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).

5.02

(6)

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6

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