IDT72413 查看數據表（PDF） - Integrated Device Technology

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IDT72413

CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

Integrated Device Technology 

IDT72413

CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

TIMING DIAGRAMS (Continued)

(2)

SHIFT OUT

(3)

SHIFT IN

INPUT READY (1)

t PT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(5)

(4)

tIPH

INPUT DATA

STABLE DATA

NOTES:

1. FIFO is initially full.

2. Shift Out pulse is applied.

3. Shift In is held HIGH.

4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.

5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH).

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

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1/fOUT

1/fOUT

SHIFT OUT

tSOH

t SOL

(2)

t RH

OUTPUT READY

tORD

t ODS

tODH

tORL

OUTPUT DATA

A-DATA

B-DATA

(1)

NOTES:

1. This data is loaded consecutively A, B, C.

2. Output data changes on the falling edge of SO after a valid Shift Out sequence, i.e., OR and SO are both high together.

Figure 5. Output TIming

C-DATA

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SHIFT OUT(7)

OUTPUT READY

(2)

(1)

(4)

(5)

(3)

(6)

OUTPUT DATA

A-DATA

B-DATA

A or B

NOTES:

1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.

2. Shift Out goes HIGH causing the next step.

3. Output Ready goes LOW.

4. Read pointer is incremented.

5. Output Ready goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns.

6. If the FIFO has only one word loaded (A DATA) , Output Ready stays LOW and the A-DATA remains unchanged at the outputs.

7. Shift Out pulses applied when Output Ready is LOW will be ignored.

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Figure 6. The Mechanism of Shifting Data Out of the FIFO

5.02

7

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