IMC002FLSA-15 查看數據表（PDF） - Intel

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IMC002FLSA-15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

WRITE PROTECTION REGISTER

(Read Write Register)

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

4104H

RESERVED FOR FUTURE USE

CMWP

CISWP

1 e WRITE PROTECT

Figure 8 WRITE PROTECTION REGISTER (Intel) Eliminates Accidental Data Corruption

SLEEP CONTROL REGISTER (INTEL)

Unlike the GLOBAL RESET-POWERDOWN REGIS-

TER which simultaneously resets and places all

flash memory devices into a Deep-Sleep mode the

SLEEP CONTROL REGISTER (Attribute Memory

Plane Address 4118H–411AH Figure 9) allows se-

lective power-down control of individual device pairs

Writing a 1 to a specific bit of the SLEEP CONTROL

REGISTER places the corresponding device pair

into the ‘‘Deep-Sleep’’ mode Devices in Deep-Sleep

are not accessible On cards with fewer than

20 Megabytes (10 device pairs) writing a one to an

absent device pair has no affect and reads back as

zero

This register contains all zeroes (i e not in Deep-

Sleep mode) when the card powers up or after a

hard or soft reset Furthermore the Global Reset-

PowerDown Register has no affect on the contents

of this register Therefore any bit settings of the

Sleep Control Register will remain unchanged after

returning from a global reset and power down (writ-

ing a zero to the RP bit of the Global Reset-Power-

Down Register)

READY-BUSY STATUS

REGISTER (INTEL)

The bits in the Read-only READY-BUSY Status

Register (Attribute Memory Plane Address 4130H-

4134H Figure 10) reflect the status (READYe1

BUSYe0) of each device’s RY BY output A busy

condition indicates that a device is currently pro-

cessing a data-write or block-erase operation

These bits are logically ‘‘AND-ed’’ to form the

Ready Busy output (RDY BSY pin 16) of the

PCMCIA interface On memory cards with fewer

than 20 devices unused Device RY BY Status

Register bits appear as ready

SLEEP CONTROL REGISTER

(Read Write Register)

ADDRESS

411AH

4118H

BIT 7

DEVICES

14 15

BIT 6

DEVICES

12 13

BIT 5

BIT 4

RESERVED

DEVICES DEVICES

10 11

89

BIT 3

DEVICES

67

BIT 2

DEVICES

45

BIT 1

DEVICES

18 19

DEVICES

23

BIT 0

DEVICES

16 17

DEVICES

01

1 e SELECTED DEVICE PAIR IN POWER-DOWN MODE AND RESET

Figure 9 SLEEP CONTROL REGISTER (Intel) Allows Specific

Devices to be Reset and Put into Power-Down Mode

13

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