IMC002FLSA-15 查看數據表（PDF） - Intel

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IMC002FLSA-15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

DEVICE STATUS REGISTER

Each 28F008SA device in the Series 2 Card con-

tains a Status Register which displays the condition

of its Write State Machine The Status Register is

read at any time by writing the Read Status com-

mand to the CUI After writing this command all sub-

sequent Read operations output data from the

Status Register until another command is written to

the CUI

Bit 7 WSM Status

This bit reflects the Ready Busy condition of the

WSM A ‘‘1’’ indicates that read block-erase or

data- write operations are available A ‘‘0’’ indicates

that write or erase operations are in progress

Bit 6 Erase Suspend Status

If an Erase Suspend command is issued during the

erase operation the WSM halts execution and sets

the WSM Status bit and the Erase Suspend Status

bit to a ‘‘1’’ This bit remains set until the device

receives an Erase Resume command at which point

the CUI resets the WSM Status bit and the Erase

Suspend Status bit

Bit 5 Erase Status

This bit will be cleared to 0 to indicate a successful

block-erasure When set to a ‘‘1’’ the WSM has

been unsuccessful at performing an erase verifica-

tion The device’s CUI only resets this bit to a ‘‘0’’ in

response to a Clear Status Register command

Bit 4 Write Status

This bit will be cleared to a 0 to indicate a successful

data-write operation When the WSM fails to write

data after receiving a write command the bit is set

to a ‘‘1’’ and can only be reset by the CUI in re-

sponse to a Clear Status Register command

Bit 3 VPP Status

During block-erase and data-write operations the

WSM monitors the output of the device’s internal

VPP detector In the event of low VPP the WSM sets

(‘‘1’’) the VPP Status bit the status bit for the opera-

tion in progress (either write or erase) The CUI re-

sets these bits in response to a Clear Status Regis-

ter command Also the WSM RY BY bit will be set

to indicate a device ready condition This bit MUST

be reset by system software (Clear Status Register

command) before further data writes or block erases

are attempted

Bit 7

WSM

Status

Bit 6

Erase

Suspend

Status

Device Status Register (Read Only Register)

Bit 5

Bit 4

Bit 3

Bit 2

Erase

Status

Write

Status

VPP

Status

Bit 1

Reserved

Bit 0

19

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