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IS42S16800A-7B 查看數據表(PDF) - Integrated Circuit Solution Inc

零件编号
产品描述 (功能)
生产厂家
IS42S16800A-7B
ICSI
Integrated Circuit Solution Inc ICSI
IS42S16800A-7B Datasheet PDF : 66 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
ISSI ®
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
BA0, BA1
CAS
CKE
CLK
CS
I/O0 to
I/O32
LDQM,
UDQM
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
I/O Pin
Input Pin
DQM0-DQM3
DQM
RAS
WE
VDDQ
VDD
VSSQ
VSS
Input Pin
Input Pin
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
I/O0 to I/O32 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. When LDQM or UDQM is HIGH, input data is masked and
cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
VSSQ is the output buffer ground.
VSS is the device internal ground.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
06/01/02

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