IS61LF12832A-6.5B3I 查看數據表（PDF） - Integrated Silicon Solution

零件编号

产品描述 (功能)

生产厂家

IS61LF12832A-6.5B3I

128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

Integrated Silicon Solution 

IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A

IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A

ISSI ®

119 BGA PACKAGE PIN CONFIGURATION

128K X 36 (TOP VIEW)

1

2

3

4

5

6

7

A

VDDQ

B

NC

A

CE2

A

ADSP

A

A

ADSC

A

A

CE2

VDDQ

NC

C

NC

A

A

VDD

A

A

NC

D

DQc

DQPc

Vss

E

DQc

DQc

Vss

F

VDDQ

G

DQc

DQc

DQc

Vss

BWc

NC

CE

OE

ADV

Vss

Vss

Vss

BWb

DQPb

DQb

DQb

DQb

DQb

DQb

VDDQ

DQb

H

DQc

DQc

Vss

GW

Vss

DQb

DQb

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQd

L

DQd

M

VDDQ

DQd

DQd

DQd

Vss

BWd

Vss

CLK

NC

BWE

Vss

BWa

Vss

DQa

DQa

DQa

DQa

DQa

VDDQ

N

DQd

DQd

Vss

A1*

Vss

DQa

DQa

P

DQd

DQPd

Vss

A0*

Vss

DQPa

DQa

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC

A

A

A

NC

ZZ

U

VDDQ

NC

NC

NC

NC

NC

VDDQ

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

Pin Name

A

Address Inputs

A0, A1

ADV

ADSP

Synchronous Burst Address Inputs

Synchronous Burst Address

Advance

Address Status Processor

ADSC

GW

Address Status Controller

Global Write Enable

CLK

Synchronous Clock

CE, CE2, CE2 Synchronous Chip Select

BWx (x=a-d) Synchronous Byte Write Controls

BWE

Byte Write Enable

Symbol

OE

ZZ

MODE

NC

DQa-DQd

DQPa-Pd

VDD

VDDQ

Vss

Pin Name

Output Enable

Power Sleep Mode

Burst Sequence Selection

No Connect

Data Inputs/Outputs

Output Power Supply

Power Supply

Output Power Supply

Ground

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00A

08/11/05

Share Link: