IS61NVVP25672-250 查看數據表（PDF） - Integrated Silicon Solution
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IS61NVVP25672-250
Integrated Silicon Solution
IS61NVVP25672-250 Datasheet PDF : 29 Pages
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IS61NVVP25672
IS61NVVP51236
ISSI ®
STATE DIAGRAM
READ
BEGIN
READ
DS
READ
READ
WRITE
DS
WRITE
BEGIN
WRITE
WRITE
READ BURST
BURST
BURST
READ
DESELECT
BURST WRITE
DS
BURST
DS
WRITE
DS
READ
BURST
WRITE
BURST
SYNCHRONOUS TRUTH TABLE(1)
Operation
Address
Used
CS1 CS2 CS2 ADV WE BWx OE CKE CLK
Not Selected Continue
N/A
X
X
X
H
X
X
X
L
↑
Not Selected
N/A
H
X
X
L
X
X
X
L
↑
Not Selected
N/A
X
L
X
L
X
X
X
L
↑
Not Selected
N/A
X
X
H
L
X
X
X
L
↑
Begin Burst Read
External Address L
H
L
L
H
X
L
L
↑
Continue Burst Read
Next Address
X
X
X
H
X
X
L
L
↑
NOP/Dummy Read
External Address L
H
L
L
H
X
H
L
↑
Dummy Read
Next Address
X
X
X
H
X
X
H
L
↑
Begin Burst Write
External Address L
H
L
L
L
L
X
L
↑
Continue Burst Write
Next Address
X
X
X
H
X
L
X
L
↑
NOP/Write Abort
N/A
L
H
L
L
L
H
X
L
↑
Write Abort
Next Address
X
X
X
H
X
H
X
L
↑
Ignore Clock
Current Address X
X
X
X
X
X
X
H
↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
ADVANCED INFORMATION Rev. 00A
07/17/02
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