KM4101IC8 查看數據表（PDF） - Fairchild Semiconductor
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KM4101IC8 Datasheet PDF : 11 Pages
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DATA SHEET
KM4100/KM4101
Overdrive Recovery
Input
RL = 2kΩ
Vin =2Vpp
G=5
Rf = 1kΩ
Output
Time (20ns/div)
Figure 4: Overdrive Recovery
Driving Capacitive Loads
The Frequency Response vs. CL plot on page 4,
illustrates the response of the KM4100 and KM4101. A
small series resistance (Rs) at the output of the amplifier,
illustrated in Figure 5, will improve stability and
settling performance. Rs values in the Frequency
Response vs. CL plot were chosen to achieve maximum
bandwidth with less than 1dB of peaking. For maximum
flatness, use a larger Rs.
Refer to the evaluation board layouts shown in Figure
7 for more information.
Evaluation Board Information
The following evaluation boards are available to aid
in the testing and layout of this device:
Eval Board
KEB002
KEB003
Description
Products
Single Channel,
KM4100IT5,
Dual Supply 5 & 6 lead SOT23 KM4101IT6
Single Channel, Dual Supply KM4100IC8,
8 lead SOIC
KM4101IC8
Evaluation board schematics and layouts are shown in
Figure 6 and Figure 7.
The KEB002 and KEB003 evaluation boards are built
for dual supply operation. Follow these steps to use
the board in a single supply application:
1. Short -Vs to ground
2. Use C3 and C4, if the -Vs pin of the KM4100 or
KM4101 is not directly connected to the
ground plane.
+
-
Rf
Rg
Rs
CL RL
Figure 5: Typical Topology for driving
a capacitive load
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. Fairchild has evaluation
boards to use as a guide for high frequency layout
and to aid in device testing and characterization.
Follow the steps below as a basis for high frequency
layout:
s Include 6.8µF and 0.01µF ceramic capacitors
s Place the 6.8µF capacitor within 0.75 inches
of the power pin
s Place the 0.01µF capacitor within 0.1 inches
of the power pin
s Remove the ground plane under and around the
part, especially near the input and output pins to
reduce parasitic capacitance
s Minimize all trace lengths to reduce
series inductances
8
Figure 6: Evaluation Board Schematic
(SOIC pinout shown)
REV. 1A February 2001
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