KM6264B 查看數據表（PDF） - Samsung

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KM6264B

8Kx8 bit Low Power CMOS Static RAM

Samsung 

KM6264B Family

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled)

(/CS=/OE=Vil, CS2=/WE=Vih)

tRC

Address

Data Out

tAA

tOH

Previous Data Valid

CMOS SRAM

Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (/WE= VIH)

Address

/CS1

t RC

tAA

tCO1

CS2

/OE

Data out

High - Z

tCO2

tOE

t OLZ

t LZ

Data Vailid

t OH

tHtHZZ(1,2)

tOHZ

Notes(Read Cycle)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not

referenced to output voltage levels.

2. At any given temperature and voltage condition, tHZ(Max) is less than tLZ(Min) both for a given device and

device to device interconnection.

7

ELECTRONICS

Revision. 0.0

Auust. 1996

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