KM6264B 查看數據表（PDF） - Samsung
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KM6264B Datasheet PDF : 10 Pages
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KM6264B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)
Address
/CS1
tAS(3)
t WC
tCW(2)
t AW
t WR2(4)
CS2
/WE
Data in
tCW(2)
tWP(1)
t DW
t DH
Data Vailid
Data out
High - Z
High - Z
Notes(Write Cycle)
1. A write occurs during the overlap of a low /CS1, a high CS2 and a low /WE. A write begins at the latest transition
among /CS1 going low, CS2 going high and /WE going low. A write ends at the earliest transition among /CS1 going
high, CS2 going low and /WE going high, tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at /CS1, or /WE
going high, tWR2 applied in case a write ends at CS2 going to low.
FUNCTIONAL DESCRIPTION
/CS1
CS2
/WE
/OE
H
X
X
X
X
L
X
X
L
H
H
H
L
H
H
L
L
H
L
X
* X means don't care
Mode
Power Down
Power Down
Output Disable
Read
Write
I/O Pin
High-Z
High-Z
High-Z
Dout
Din
Current Mode
Isb, Isb1
Isb, Isb1
Icc
Icc
Icc
9
ELECTRONICS
Revision. 0.0
Auust. 1996
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