LH28F160S5-L/S5H-L
Table 2.1 Bus Operations (BYTE# = VIH)
MODE
NOTE RP# CE0# CE1# OE# WE# ADDRESS VPP DQ0-15 STS
Read
1, 2, 3, 9 VIH
VIL
VIL
VIL
VIH
X
X
DOUT
X
Output Disable
3
VIH
VIL
VIL
VIH
VIH
X
X High Z X
VIH
VIH
Standby
3
VIH
VIH
VIL
X
X
X
X High Z X
VIL
VIH
Deep Power-Down
4
VIL
X
X
X
X
X
X High Z High Z
Read Identifier
Codes
9
VIH
VIL
VIL
VIL
VIH
See
X (NOTE 5) High Z
Fig. 2
Query
Write
9
VIH
VIL
VIL
VIL
VIH See Table X (NOTE 6) High Z
6 through 10
3, 7, 8, 9 VIH
VIL
VIL
VIH
VIL
X
X
DIN
X
Table 2.2 Bus Operations (BYTE# = VIL)
MODE
NOTE RP# CE0# CE1# OE# WE# ADDRESS VPP DQ0-7 STS
Read
1, 2, 3, 9 VIH
VIL
VIL
VIL
VIH
X
X
DOUT
X
Output Disable
3
VIH
VIL
VIL
VIH
VIH
X
X High Z X
VIH
VIH
Standby
3
VIH
VIH
VIL
X
X
X
X High Z X
VIL
VIH
Deep Power-Down
4
VIL
X
X
X
X
X
X High Z High Z
Read Identifier
Codes
9
VIH
VIL
VIL
VIL
VIH
See
X (NOTE 5) High Z
Fig. 2
Query
9
VIH
VIL
VIL
VIL
VIH See Table X (NOTE 6) High Z
6 through 10
Write
3, 7, 8, 9 VIH
VIL
VIL
VIH
VIL
X
X
DIN
X
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
2. X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1 voltages.
3. STS is VOL (if configured to RY/BY# mode) when the
WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
algorithms. It is floated during when the WSM is not
4. RP# at GND±0.2 V ensures the lowest deep power-
down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when VPP = VPPH1 and VCC = VCC1/2.
8. Refer to Table 3 for valid DIN during a write operation.
9. Don’t use the timing both OE# and WE# are VIL.
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.
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