LH28F160S5-L70 查看數據表（PDF） - Sharp Electronics
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LH28F160S5-L70
Sharp Electronics
LH28F160S5-L70 Datasheet PDF : 55 Pages
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LH28F160S5-L/S5H-L
PIN DESCRIPTION
SYMBOL
TYPE
A0-A20
INPUT
DQ0-DQ15
INPUT/
OUTPUT
CE0#, CE1# INPUT
RP#
OE#
WE#
INPUT
INPUT
INPUT
OPEN
STS
DRAIN
OUTPUT
WP#
BYTE#
INPUT
INPUT
VPP
SUPPLY
VCC
GND
NC
SUPPLY
SUPPLY
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
A0 : Byte Select Address. Not used in x16 mode (can be floated).
A1-A4 : Column Address. Selects 1 of 16-bit lines.
A5-A15 : Row Address. Selects 1 of 2 048-word lines.
A16-A20 : Block Address.
DATA INPUT/OUTPUTS :
DQ0-DQ7 : Inputs data and commands during CUI write cycles; outputs data during
memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ8-DQ15 : Inputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode (BYTE# = VIL). Data is internally latched during a write cycle.
CHIP ENABLE : Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE0# or CE1# VIH deselects the device and reduces power
consumption to standby levels. Both CE0# and CE1# must be VIL to select the devices.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE : Gates the device’s outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level
mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table 3 and Section 4.14).
WRITE PROTECT : Master control for block locking. When VIL, locked blocks can not
be erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE : BYTE# VIL places device in x8 mode. All data are then input or output
on DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode, and turns off the
A0 input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or
configuring block lock-bits. With VPP ≤ VPPLK, memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an
invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 5 V operation.
Do not float any power pins. With VCC ≤ VLKO, all write attempts to the flash memory
are inhibited. Device operations at invalid VCC voltage (see Section 6.2.3 "DC
CHARACTERISTICS") produce spurious results and should not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
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