LH28F160S5R-L90 查看數據表（PDF） - Sharp Electronics

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LH28F160S5R-L90

16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)

Sharp Electronics 

1 INTRODUCTION

This datasheet contains LH28F160S5-L/S5H-L

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4, and 5 describe the

memory organization and functionality. Section 6

covers electrical specifications. LH28F160S5-L/

S5H-L flash memories documentation also includes

ordering information which is referenced in

Section 7.

1.1 Product Overview

The LH28F160S5-L/S5H-L are high-performance

16 M-bit Smart 5 flash memories organized as

2 MB x 8/1 MB x 16. The 2 MB of data is arranged

in thirty-two 64 k-byte blocks which are individually

erasable, lockable, and unlockable in-system. The

memory map is shown in Fig.1.

Smart 5 technology provides a choice of VCC and

VPP combination, as shown in Table 1, to meet

system performance and power expectations. VPP

at 5 V eliminates the need for a separate 12 V

converter, while VPP = 5 V maximizes erase and

write performance. In addition to flexible erase and

program voltages, the dedicated VPP pin gives

complete data protection when VPP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combination

Offered by Smart 5 Technology

VCC VOLTAGE

5V

VPP VOLTAGE

5V

Internal VCC and VPP detection circuitry auto-

matically configures the device for optimized read

and write operations.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal operation of the device. A valid command

sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for block erase, full chip erase, (multi)

LH28F160S5-L/S5H-L

word/byte write and block lock-bit configuration

operations.

A block erase operation erases one of the device’s

64 k-byte blocks typically within 0.34 second (5 V

VCC, 5 V VPP) independent of other blocks. Each

block can be independently erased 100 000 times

(3.2 million block erases per device). Block erase

suspend mode allows system software to suspend

block erase to read data from, or write data to any

other block.

A word/byte write is performed in byte increments

typically within 9.24 µs (5 V VCC, 5 V VPP). A multi

word/byte write has high speed write performance

of 2 µs/byte (5 V VCC, 5 V VPP). (Multi) word/byte

write suspend mode enables the system to read

data from, or write data to any other flash memory

array location.

Individual block locking uses a combination of bits

and WP#, thirty-two block lock-bits, to lock and

unlock blocks. Block lock-bits gate block erase, full

chip erase and (multi) word/byte write operations.

Block lock-bit configuration operations (Set Block

Lock-Bit and Clear Block Lock-Bits commands) set

and cleared block lock-bits.

The status register indicates when the WSM’s block

erase, full chip erase, (multi) word/byte write or

block lock-bit configuration operation is finished.

The STS output gives an additional indicator of

WSM activity by providing both a hardware signal

of status (versus software polling) and status

masking (interrupt masking for background block

erase, for example). Status polling using STS

minimizes both CPU overhead and system power

consumption. STS pin can be configured to

different states using the Configuration command.

The STS pin defaults to RY/BY# operation. When

low, STS indicates that the WSM is performing a

-6-

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