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LH28F160S5HR-L90 查看數據表(PDF) - Sharp Electronics

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LH28F160S5HR-L90 Datasheet PDF : 55 Pages
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block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
erase is suspended and (multi) word/byte write are
inactive, (multi) word/byte write are suspended, or
the device is in deep power-down mode. The other
3 alternate configurations are all pulse mode for
use as a system interrupt.
The access time is 70 ns (tAVQV) at the VCC supply
voltage range of 4.75 to 5.25 V over the temperature
range, 0 to +70°C (LH28F160S5-L)/40 to +85°C
(LH28F160S5H-L). At 4.5 to 5.5 V VCC, the access
time is 80 ns/100 ns (LH28F160S5-L70/S5-L10) or
90 ns/100 ns (LH28F160S5H-L70/S5H-L10).
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA at
5 V VCC.
When either CE0# or CE1#, and RP# pins are at
VCC, the ICC CMOS standby mode is enabled.
When the RP# pin is at GND, deep power-down
mode is enabled which minimizes power
consumption and provides write protection during
reset. A reset time (tPHQV) is required from RP#
switching high until outputs are valid. Likewise, the
device has a wake time (tPHEL) from RP#-high until
writes to the CUI are recognized. With RP# at
GND, the WSM is reset and the status register is
cleared.
LH28F160S5-L/S5H-L
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Fig. 1 Memory Map
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