M25P05-VMN6T 查看數據表（PDF） - STMicroelectronics

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M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

Figure 15. Bulk Erase (BE) Sequence

M25P05

S

01234567

C

Instruction

D

AI03752C

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1

(FFh). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write En-

able Latch (WEL).

The Bulk Erase (BE) instruction is entered by driv-

ing Chip Select (S) Low, followed by the instruction

code on Serial Data Input (D). Chip Select (S)

must be driven Low for the entire duration of the

sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the

eighth bit of the instruction code has been latched

in, otherwise the Bulk Erase instruction is not exe-

cuted. As soon as Chip Select (S) is driven High,

the self-timed Bulk Erase cycle (whose duration is

tBE) is initiated. While the Bulk Erase cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-

timed Bulk Erase cycle, and is 0 when it is com-

pleted. At some unspecified time before the cycle

is completed, the Write Enable Latch (WEL) bit is

reset.

The Bulk Erase (BE) instruction is executed only if

both Block Protect (BP1, BP0) bits are 0. The Bulk

Erase (BE) instruction is ignored if one, or more,

sectors are protected.

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