M25P05-VMN6T 查看數據表（PDF） - STMicroelectronics

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M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

M25P05

Figure 18. Release from Deep Power-down (RES) Sequence

S

01234567

tRES

C

Instruction

D

High Impedance

Q

Deep Power-down Mode Stand-by Mode

AI03754C

Driving Chip Select (S) High after the 8-bit instruc-

tion byte has been received by the device, but be-

fore the whole of the 8-bit Electronic Signature has

been transmitted for the first time (as shown in Fig-

ure 18), still insures that the device is taken out of

the Deep Power-down mode, but incurs a delay

(tRES) before the device is put in Standby mode.

Chip Select (S) must remain High for at least

tRES(max), as specified in Table 14.

20/32

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