M5M5W816TP-55HI 查看數據表（PDF） - Renesas Electronics

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M5M5W816TP-55HI

8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

Renesas Electronics 

2002.08.30 Ver. 6.1

M5M5W816TP - 55HI, 70HI, 85HI

MITSUBISHI LSIs

Write cycle (BC# control mode)

A 0~18

BC1#,BC2#

tsu (A)

8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

tCW

tsu (BC1) or

tsu (BC2)

trec (W)

S#

W#

DQ1~16

(Note3)

(Note5)

(Note3)

(Note4)

tsu (D) th (D)

DATA IN

STABLE

(Note3)

(Note3)

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S# low ov erlaps BC1# and/or BC2# low and W# low.

Note 5: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of

S#, the outputs are maintained in the high impedance state.

Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.

6

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