M5M5V408BFP 查看數據表（PDF） - Renesas Electronics
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M5M5V408BFP Datasheet PDF : 10 Pages
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rev. 3.0e, Feb. 12, 2001
M5M5V408BFP,TP,KV
MITSUBISHI LSIs
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S# control mode)
A 0~18
S#
tsu (A)
tCW
tsu (S)
(Note4)
W#
DQ1~8
(Note3)
(Note5)
(Note4)
(Note6)
tsu (D) th (D)
DATA IN
STABLE
trec (W)
(Note3)
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during the ov erlap of a low S# and a low W#.
Note 5: If W# goes low simultaneously with or prior to S#,the output remains in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
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