M62420SP 查看數據表（PDF） - Renesas Electronics

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M62420SP

2ch Electronic Volume with Tone by I2C Bus System

Renesas Electronics 

M62420SP/ FP/ AFP

BUS Line Timing Specification

tR, tF

tBUF

VIL

SDA

VIH

VIL

SCL

VIH

tHD:STA

S

tSU:DAT

tHD:DAT

tLOW

tHIGH

tSU:STA

S

tSU:STO

P

Parameter

Min. input low voltage

Max. input high voltage

SCL clock frequency

Time the bus must be free before a new transmission can start

Hold time start condition. After this period the first clock pulse is generated

The LOW period of the clock

The HIGH period of the clock

Set up time for start condition (Only relevant for a repeated start condition)

Hold time DATA

Set-up time DATA

Rise time of both SDA and SCL lines

Fall time of both SDA and SCL lines

Set-up time for stop condition

Symbol

VIL

VIH

fSCL

tBUF

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

tF

tSU:STO

MIN

–0.5

3.0

0

4.7

4.0

4.7

4.0

4.7

0

250

4.0

MAX

1.5

5.5

100

1000

300

S

Units

V

V

kHz

µs

µs

µs

µs

µs

µs

ns

ns

ns

µs

Rev.1.0, Sep.17.2003, page 11 of 16

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