MAX1072CTC-T(2004) 查看數據表（PDF） - Maxim Integrated
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MAX1072CTC-T
(Rev.:2004)
(Rev.:2004)
Maxim Integrated
MAX1072CTC-T Datasheet PDF : 18 Pages
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1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
CNVST
SCLK
tSETUP
12
34
POWER-MODE SELECTION WINDOW
8
tACQUIRE
CONTINUOUS-CONVERSION
14
16 SELECTION WINDOW
HIGH IMPEDANCE
DOUT
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
Figure 5. Interface-Timing Sequence
CNVST
SCLK
DOUT
MODE
ONE 8-BIT TRANSFER
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
1ST SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
0
0
0 D9 D8 D7 D6 D5
NORMAL
PPD
Figure 6. SPI Interface—Partial Power-Down Mode
CNVST
SCLK
DOUT
(MODE)
FIRST 8-BIT TRANSFER
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
0
0
0 D9 D8 D7 D6 D5
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
0
0
0
0
0
0
0
NORMAL
PPD
RECOVERY
FPD
Figure 7. SPI Interface—Full Power-Down Mode
power-down mode. Then repeat the same sequence to
enter full power-down mode (see Figure 7). Drive CNVST
low, and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit full power-down mode. In par-
tial/full power-down mode, maintain a logic low or a logic
high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1072. Figure 9 shows the bipolar transfer function for
the MAX1075. The MAX1072 output is straight binary,
while the MAX1075 output is two’s complement.
10 ______________________________________________________________________________________
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